Conventional semiconductor devices comprise a semiconductor wafer, normally monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive layers on the wafer frontside, with integrated circuity containing a plurality of conductive patterns comprising spaced apart conductive lines, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, conductive patterns in different layers, i.e., upper and lower layers, are electrically connected by conductive vias; while electrical connection to an active region on the frontside of the wafer is effected by a contact hole filled with conductive material, such as a metal.
Conductive vias and contacts are typically formed by depositing a dielectric layer, forming an opening therethrough by conventional photolithographic techniques, and filling the opening with a conductive material, such as tungsten. One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal, such as tungsten, to form an interconnecting contact or via plug. Damascene techniques are also conventionally employed to form conductive patterns of closely spaced apart conductive lines by employing photolithographic and etching techniques to form a plurality of trenches, for example, substantially horizontal trenches, in a dielectric layer, which trenches are subsequently filled with a metal. In copending application Ser. No. 08/320,516 filed on Oct. 11, 1994, prior art single and dual damascene techniques are disclosed, in addition to several improved dual damascene techniques for greater accuracy in forming fine line patterns with minimal interwiring spacings.
Conventional practices for forming vias and contacts by etching an opening through a dielectric layer and filling the opening with a metal involve complicated manipulative steps and are attendant with numerous disadvantages. Various problems stem from photolithographic techniques to form openings, etching and filling the openings, particularly in forming openings with submicron dimensions to satisfy increased densification requirements and performance in ultra-large scale integration semiconductor technology. Such problems lead to unreliable electrical contact, lower operating speeds and poor signal-to-noise ratios.
As the design requirements for interconnection patterns become more severe, requiring increasingly smaller dimensions for through holes, conductive line widths and interwiring spacings, such as less than about 0.30 .mu.m, particularly less than about 0.25 .mu.m, the ability of conventional photolithographic techniques to satisfy such demands with satisfactory accuracy becomes increasingly more difficult. The limitation on achieving such fine dimensions resides in the inability of conventional photolithographic techniques to satisfy the accuracy requirement for such fine patterns.
In forming patterns having a small dimension, such as about 0.30 to about 0.40 .mu.m or greater, I-line photolithography is conventionally employed. As the maximum dimension is reduced, e.g., to below about 0.30 .mu.m, such as less than about 0.25 .mu.m, it is necessary to resort to shorter wavelengths, such as deep ultra-violet light. It is, however, very difficult to form fine line patterns with a maximum dimension of about 0.30 .mu.m or less with any reasonable degree of accuracy, consistency and efficiency. Thus, there is a need for reducing photolithographic failure, particularly in printing contact holes and vias having a submicron dimension below about 0.30 .mu.m, particularly below 0.25 .mu.m.